This invention relates generally to high speed semiconductor memory, and more specifically to methods and apparatus for reducing layout space, power consumption and noise reduction related to delay lines for command paths. Semiconductor memories typically include an array of memory cells, address decoding circuitry for selecting one of or a group of the memory cells for reading or writing data, sensing circuitry for detecting the digital state of the selected memory cell(s), and input/output lines to receive the sensed data and convey that information for eventual output from the semiconductor memory. Synchronous memories receive and deliver data coincident with a clock signal. Conventionally, an external clock signal is received by the device. Input signals and data are received synchronized with the external clock signal. Due to internal delays associated with the components of the memory, the phase of the external clock signal is shifted within the memory. Timing control circuits, such as delay-locked loops (DLLs) or phase locked loops (PLLs), may be provided for synchronizing the output signals and the output strobe signals with the provided external clock signal.
The timing control circuits may also be utilized by the memory due to the memory internally operating at a different clock rate than that of the external clock signal. An internal clock signal of the memory may be based on the external clock signal, half the external clock rate for example. Because the memories may operate at a clock rate that is slower than the external clock rate, commands received by the memory may be broken up and processed in parallel so that output of the memory is synchronized with the external clock and released onto output lines at an expected time. For example, an external component may request a read command from the memory and expect to receive the data at a certain number of external clock cycles after sending the command, e.g., 8 external clock cycles. Due to the break up and parallel operation of the command, however, the data may be accessed in less than 8 external clock cycles even though the memory is operating at half that rate. To ensure the data is buffered onto the output lines at the anticipated time, the timing control circuit may include internal delays that slow down the access and/or release of the data.
The internal delays may occur in various circuits of the memory, such as a DLL. The DLL may delay command signals, and the internal and external clock signals of the memory. By implementing the DLL on both the command signals and clock signals, the DLL may ensure that all those associated signals for a command are commensurately delayed so that the output is placed on the output lines at the correct time. Delaying all of those signals, however, may require additional on-die real estate since the command path may need 20 to 40 delay line replicas. In addition to the on-die real estate consumed by the delay line replicas, the power consumption may increase along with signal noise.